A plasma display panel includes: an upper substrate; an upper dielectric layer formed on a lower surface of the upper substrate; sustain electrodes disposed in the upper dielectric layer; a lower substrate facing the upper substrate; a lower dielectric layer formed on an upper surface of the lower substrate; address electrodes formed in the lower dielectric layer so as to cross the sustain electrodes; main barrier ribs disposed on the lower dielectric layer so as to define discharge cells corresponding to regions where the sustain electrodes and the address electrodes cross each other; a phosphor layer formed in the discharge cells; and dummy barrier ribs disposed at an outermost portion of the main barrier ribs, and including respective dummy units which protrude from the main barrier ribs toward an outer portion, and which are connected to each other. The connection portions between the dummy units are disposed so as to overlap with at least one of terminal units of the sustain electrodes and terminal units of the address electrodes.