发明授权
- 专利标题: Logic block control architectures for programmable logic devices
- 专利标题(中): 用于可编程逻辑器件的逻辑块控制架构
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申请号: US11446351申请日: 2006-06-02
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公开(公告)号: US07397276B1公开(公告)日: 2008-07-08
- 发明人: Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
- 申请人: Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
- 申请人地址: US OR Hillsboro
- 专利权人: Lattice Semiconductor Corporation
- 当前专利权人: Lattice Semiconductor Corporation
- 当前专利权人地址: US OR Hillsboro
- 代理机构: MacPherson Kwok Chen & Heid LLP
- 代理商 Greg J. Michelson
- 主分类号: H03K19/177
- IPC分类号: H03K19/177
摘要:
Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.
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