发明授权
US07401189B2 Pipelining D states for MRU steerage during MRU/LRU member allocation
失效
在MRU / LRU成员分配过程中,管理MRU操纵的D状态
- 专利标题: Pipelining D states for MRU steerage during MRU/LRU member allocation
- 专利标题(中): 在MRU / LRU成员分配过程中,管理MRU操纵的D状态
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申请号: US11054067申请日: 2005-02-09
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公开(公告)号: US07401189B2公开(公告)日: 2008-07-15
- 发明人: Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
- 申请人: Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Dillon & Yudell LLP
- 代理商 Diana R. Gerhardt
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F13/00 ; G06F13/28
摘要:
A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
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