发明授权
US07415692B1 Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
有权
使用执行乘法和其他算术功能的程序段编程可编程逻辑器件的方法
- 专利标题: Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
- 专利标题(中): 使用执行乘法和其他算术功能的程序段编程可编程逻辑器件的方法
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申请号: US11223193申请日: 2005-09-08
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公开(公告)号: US07415692B1公开(公告)日: 2008-08-19
- 发明人: Jennifer Farrugia , Elias Ahmed , Mark Bourgeault
- 申请人: Jennifer Farrugia , Elias Ahmed , Mark Bourgeault
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ropes & Gray LLP
- 代理商 Jeffrey H. Ingerman
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A programming method efficiently programs programmable logic devices of the type having specialized multiplier blocks that include multipliers and other arithmetic function elements. Such blocks can be used to perform certain multiplication and multiplication-related functions more efficiently than general-purpose programmable logic. In order to efficiently program devices having such specialized multiplier blocks, so that they are used to their full potential and so that the maximum number of multiplier-related functions can be accommodated on a single programmable logic device, the programming method pre-processes the netlist of function blocks in a user's programmable logic design, grouping multiplication and multiplication-related functions efficiently. The method takes into account limitations imposed by the structure of the specialized multiplier blocks, in addition to location constraints imposed by the user and location constraints dictated by the need for certain functions be carried out near where certain other functions are carried out.
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