A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.