Invention Grant
- Patent Title: Memory module with parallel testing
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Application No.: US11811551Application Date: 2007-06-11
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Publication No.: US07441167B2Publication Date: 2008-10-21
- Inventor: Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
- Applicant: Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agent Monica H. Choi
- Priority: KR2004-19628 20040323; KR2004-70025 20040902
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.
Public/Granted literature
- US20080005631A1 Memory module with parallel testing Public/Granted day:2008-01-03
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