发明授权
- 专利标题： Contact resistance and capacitance for semiconductor devices
- 专利标题（中）： 半导体器件的接触电阻和电容
-
申请号： US11440657申请日： 2006-05-24
-
公开(公告)号： US07441218B2公开(公告)日： 2008-10-21
- 发明人: Nagaraj N. Savithri , Dharin Nayeshbhai Shah , Girishankar Gurumurthy
- 申请人： Nagaraj N. Savithri , Dharin Nayeshbhai Shah , Girishankar Gurumurthy
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
公开/授权文献
信息查询
