发明授权
US07447879B2 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss
有权
在级联的延迟执行流水线中调度指令以最小化由缓存未命中引起的流水线停顿
- 专利标题： Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss
- 专利标题（中）： 在级联的延迟执行流水线中调度指令以最小化由缓存未命中引起的流水线停顿
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申请号： US11351247申请日： 2006-02-09
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公开(公告)号： US07447879B2公开(公告)日： 2008-11-04
- 发明人: David A. Luick
- 申请人： David A. Luick
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Patterson & Sheridan LLP
- 主分类号： G06F9/30
- IPC分类号： G06F9/30
摘要：
A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group is a load instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is not delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
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