Invention Grant
US07454555B2 Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device
失效
装置和方法包括具有多组存储器组的存储器件,具有模拟快速存取时间的复制数据,固定延迟存储器件
- Patent Title: Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device
- Patent Title (中): 装置和方法包括具有多组存储器组的存储器件,具有模拟快速存取时间的复制数据,固定延迟存储器件
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Application No.: US10865398Application Date: 2004-06-10
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Publication No.: US07454555B2Publication Date: 2008-11-18
- Inventor: Frederick A. Ware , Ely Tsern , Steven Woo , Richard E. Perego
- Applicant: Frederick A. Ware , Ely Tsern , Steven Woo , Richard E. Perego
- Applicant Address: US CA Los Altos
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Los Altos
- Agency: Vierra Magen Marcus & DeNiro LLP
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive fast-cycle, fixed latency single memory device. In an embodiment of the invention, a memory controller includes controller logic and a plurality of write buffers for interleaving write transactions to each memory bank in the two memory devices. A memory controller also includes tag memory for identifying valid data in the memory banks. In another embodiment of the invention, a game console includes the apparatus and executes game software that requires fixed latency in a mode of operation. In yet another embodiment of the invention, each memory device is coupled to respective write channels. Write data is simultaneously written to two memory banks in respective sets of memory banks in a memory device in an embodiment of the present invention. In an alternate embodiment of the present invention, an apparatus includes four memory devices for storing duplicate data with each memory device having a set of memory banks. The four memory devices are coupled to a controller by four respective write channels.
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