A DMA controller is connected by a bus to a plurality of master devices and a plurality of slave devices, and performs a data transfer between slave devices which are specified as a source and a destination of the data transfer by a transfer condition received from any of the plurality of master devices. Each of the plurality of master devices and the plurality of slave devices has a rank used for judging data transfer permissibility. The DMA controller enables the data transfer if the data transfer is judged to be permitted as a result of a comparison between a rank of the master device and a rank of any of the specified slave devices, and disables the data transfer if the data transfer is judged to be prohibited.