A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.