发明授权
- 专利标题: Method for manufacturing integrated circuit
- 专利标题(中): 集成电路制造方法
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申请号: US11790230申请日: 2007-04-24
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公开(公告)号: US07462567B2公开(公告)日: 2008-12-09
- 发明人: Tetsuya Yamada , Tsutomu Imai
- 申请人: Tetsuya Yamada , Tsutomu Imai
- 申请人地址: JP Moriguchi
- 专利权人: Sanyo Electric Co., Ltd.
- 当前专利权人: Sanyo Electric Co., Ltd.
- 当前专利权人地址: JP Moriguchi
- 代理机构: Oliif & Berridge, PLC
- 优先权: JP2006-122520 20060426
- 主分类号: H01L21/302
- IPC分类号: H01L21/302 ; H01L21/461
摘要:
The flatness of the surface of the light-receiving portion must be increased when the upper structural layer of a light detector is etched. The present invention provides a method for manufacturing an integrated circuit in which an aperture is formed in a stack in which an underlayer, a light-receiving area pad, and an upper structural layer are layered on a substrate, the method comprising a light-receiving area pad etching step for etching the structural layer and the light-receiving area pad under etching conditions in which a high selectivity ratio is maintained between the upper structural layer and the light-receiving area pad; and an underlayer etching step for switching to etching conditions in which the light-receiving area pad has a high selectivity ratio in relation to the underlayer following the light-receiving area pad etching step, and etching the light-receiving area pad and the underlayer. The bottom surface of the aperture can thereby be made flatter and the amount of incident light in the plane of the light-receiving portion can be made more uniform.
公开/授权文献
- US20070254400A1 Method for manufacturing integrated circuit 公开/授权日:2007-11-01