Invention Grant
US07465660B2 Graded/stepped silicide process to improve MOS transistor 有权
分级/步进硅化处理以改善MOS晶体管

  • Patent Title: Graded/stepped silicide process to improve MOS transistor
  • Patent Title (中): 分级/步进硅化处理以改善MOS晶体管
  • Application No.: US10424800
    Application Date: 2003-04-28
  • Publication No.: US07465660B2
    Publication Date: 2008-12-16
  • Inventor: Fuchao WangMing Fang
  • Applicant: Fuchao WangMing Fang
  • Applicant Address: US TX Carrollton
  • Assignee: STMicroelectronics, Inc.
  • Current Assignee: STMicroelectronics, Inc.
  • Current Assignee Address: US TX Carrollton
  • Agent Lisa K. Jorgenson; William A. Munck
  • Main IPC: H01L21/44
  • IPC: H01L21/44
Graded/stepped silicide process to improve MOS transistor
Abstract:
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.
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