发明授权
- 专利标题: Processor instruction retry recovery
- 专利标题(中): 处理器指令重试恢复
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申请号: US11055258申请日: 2005-02-10
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公开(公告)号: US07467325B2公开(公告)日: 2008-12-16
- 发明人: Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
- 申请人: Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Duke W. Yee; Diana L. Roberts-Gerhardt; Gerald H. Glanzman
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
公开/授权文献
- US20060179207A1 Processor instruction retry recovery 公开/授权日:2006-08-10