发明授权
US07468301B2 PMOS transistor with increased effective channel length in the peripheral region and a multi-height substrate
有权
PMOS晶体管，其在周边区域中具有增加的有效沟道长度和多高度衬底
- 专利标题： PMOS transistor with increased effective channel length in the peripheral region and a multi-height substrate
- 专利标题（中）： PMOS晶体管，其在周边区域中具有增加的有效沟道长度和多高度衬底
-
申请号： US11302055申请日： 2005-12-12
-
公开(公告)号： US07468301B2公开(公告)日： 2008-12-23
- 发明人: Jin Yul Lee
- 申请人： Jin Yul Lee
- 申请人地址： KR Kyoungki-do
- 专利权人： Hynix Semiconductor Inc.
- 当前专利权人： Hynix Semiconductor Inc.
- 当前专利权人地址： KR Kyoungki-do
- 代理机构： Ladas & Parry LLP
- 优先权： KR10-2005-0014860 20050223
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L29/80
摘要：
In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.
公开/授权文献
信息查询
IPC分类:
