发明授权
US07469399B2 Semi-flattened pin optimization process for hierarchical physical designs
失效
半平面针脚优化过程,用于分层物理设计
- 专利标题: Semi-flattened pin optimization process for hierarchical physical designs
- 专利标题(中): 半平面针脚优化过程,用于分层物理设计
-
申请号: US11531398申请日: 2006-09-13
-
公开(公告)号: US07469399B2公开(公告)日: 2008-12-23
- 发明人: Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
- 申请人: Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Lynn L. Augspurger; L. J. Marhoefer
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/45
摘要:
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
公开/授权文献
信息查询