发明授权
US07469399B2 Semi-flattened pin optimization process for hierarchical physical designs 失效
半平面针脚优化过程,用于分层物理设计

Semi-flattened pin optimization process for hierarchical physical designs
摘要:
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
信息查询
0/0