发明授权
- 专利标题： Optimized circuits for three dimensional packaging and methods of manufacture therefore
- 专利标题（中）： 因此，用于三维包装的优化电路和制造方法
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申请号： US11353930申请日： 2006-02-14
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公开(公告)号： US07471146B2公开(公告)日： 2008-12-30
- 发明人: William Macropoulos , Greg Mendolia , James G. Oakes , Izz Khayo
- 申请人： William Macropoulos , Greg Mendolia , James G. Oakes , Izz Khayo
- 申请人地址： US MO Columbia
- 专利权人： Paratek Microwave, Inc.
- 当前专利权人： Paratek Microwave, Inc.
- 当前专利权人地址： US MO Columbia
- 代理商 James S. Finn, Esq.
- 主分类号： H03G3/00
- IPC分类号： H03G3/00 ; H03G3/20
摘要：
An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.