发明授权
US07474588B2 Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same
失效
用于集成电路存储器件的数据输出电路，其中响应于多个时钟信号的选择性调用而输出数据，以及操作其的方法
- 专利标题： Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same
- 专利标题（中）： 用于集成电路存储器件的数据输出电路，其中响应于多个时钟信号的选择性调用而输出数据，以及操作其的方法
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申请号： US11755165申请日： 2007-05-30
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公开(公告)号： US07474588B2公开(公告)日： 2009-01-06
- 发明人: Sung-Ryul Kim
- 申请人： Sung-Ryul Kim
- 申请人地址： KR Gyeonggi-do
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR Gyeonggi-do
- 代理机构： Myers Bigel Sibley & Sajovec, P.A.
- 优先权： KR10-2006-0051985 20060609
- 主分类号： G11C8/18
- IPC分类号： G11C8/18
摘要：
A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals thereof onto an output terminal responsive to selective invocation of the plurality of clock signals. The clock signals are invoked in an order based on the at least a portion of the memory column address.
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