发明授权
- 专利标题： Frame alteration logic for network processors
- 专利标题（中）： 网络处理器的帧更改逻辑
-
申请号： US10364069申请日： 2003-02-11
-
公开(公告)号： US07474672B2公开(公告)日： 2009-01-06
- 发明人: Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Vaidhyanathan , Johan G. A. Verkinderen
- 申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Vaidhyanathan , Johan G. A. Verkinderen
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Sawyer Law Group LLP
- 主分类号： H04J3/22
- IPC分类号： H04J3/22
摘要：
Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
公开/授权文献
- US20040156368A1 Frame alteration logic for network processors 公开/授权日：2004-08-12
信息查询
