发明授权
US07479413B2 Method for fabricating semiconductor package with circuit side polymer layer 有权
具有电路侧聚合物层的半导体封装的制造方法

  • 专利标题: Method for fabricating semiconductor package with circuit side polymer layer
  • 专利标题(中): 具有电路侧聚合物层的半导体封装的制造方法
  • 申请号: US11242224
    申请日: 2005-10-03
  • 公开(公告)号: US07479413B2
    公开(公告)日: 2009-01-20
  • 发明人: Mike ConnellTongbi Jiang
  • 申请人: Mike ConnellTongbi Jiang
  • 申请人地址: US ID Boise
  • 专利权人: Micron Technology, Inc.
  • 当前专利权人: Micron Technology, Inc.
  • 当前专利权人地址: US ID Boise
  • 代理商 Stephen A. Gratton
  • 主分类号: H01L21/00
  • IPC分类号: H01L21/00
Method for fabricating semiconductor package with circuit side polymer layer
摘要:
A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
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