Invention Grant
- Patent Title: Manufacturing process for a transistor made of thin layers
- Patent Title (中): 由薄层制成的晶体管的制造工艺
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Application No.: US11223089Application Date: 2005-09-09
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Publication No.: US07491644B2Publication Date: 2009-02-17
- Inventor: Maud Vinet , Pascal Besson , Bernard Previtali , Christian Vizioz
- Applicant: Maud Vinet , Pascal Besson , Bernard Previtali , Christian Vizioz
- Applicant Address: FR Paris FR Montrouge
- Assignee: Commissariat a l'Energie Atomique,ST Microelectronics SA
- Current Assignee: Commissariat a l'Energie Atomique,ST Microelectronics SA
- Current Assignee Address: FR Paris FR Montrouge
- Agency: Brinks Hofer Gilson & Lione
- Priority: FR0409637 20040910; FR0409894 20040917
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.
Public/Granted literature
- US20070173064A1 Manufacturing process for a transistor made of thin layers Public/Granted day:2007-07-26
Information query
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