发明授权
- 专利标题： Semiconductor arrangement
- 专利标题（中）： 半导体安排
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申请号： US11733930申请日： 2007-04-11
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公开(公告)号： US07498194B2公开(公告)日： 2009-03-03
- 发明人: Nikolaus Bott , Oliver Haeberlen , Manfred Kotek , Joost Larik , Josef Maerz , Ralf Otremba
- 申请人： Nikolaus Bott , Oliver Haeberlen , Manfred Kotek , Joost Larik , Josef Maerz , Ralf Otremba
- 申请人地址： DE Munich
- 专利权人： Infineon Technologies AG
- 当前专利权人： Infineon Technologies AG
- 当前专利权人地址： DE Munich
- 代理机构： Dicke, Billig & Czaja, PLLC
- 优先权： DE10323007 20030521
- 主分类号： H01L21/44
- IPC分类号： H01L21/44
摘要：
The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
公开/授权文献
- US20070178624A1 Semiconductor Arrangement 公开/授权日：2007-08-02
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