Invention Grant
- Patent Title: Local interconnection method and structure for use in semiconductor device
- Patent Title (中): 用于半导体器件的局部互连方法和结构
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Application No.: US11679722Application Date: 2007-02-27
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Publication No.: US07498253B2Publication Date: 2009-03-03
- Inventor: Sung-Un Kwon , Yong-Sun Ko
- Applicant: Sung-Un Kwon , Yong-Sun Ko
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR2003-35875 20030604
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.
Public/Granted literature
- US20070141834A1 LOCAL INTERCONNECTION METHOD AND STRUCTURE FOR USE IN SEMICONDUCTOR DEVICE Public/Granted day:2007-06-21
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