A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.