发明授权
- 专利标题： Electrostatic discharge testing method and semiconductor device fabrication method
- 专利标题（中）： 静电放电测试方法和半导体器件制造方法
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申请号： US11243355申请日： 2005-10-03
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公开(公告)号： US07512916B2公开(公告)日： 2009-03-31
- 发明人: Sachio Hayashi
- 申请人： Sachio Hayashi
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： DLA Piper US LLP
- 优先权： JPP2004-294961 20041007
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; H02H9/00
摘要：
A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, includes extracting an electrostatic discharge protection network including pads, nets and protective elements; setting start pads and end pads in the electrostatic discharge protection network; finding inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths from the start pads to the end pads; grouping together the electrostatic discharge current paths in the same order; calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads and groups to which the start pads and the end pads belong using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages; and determining whether the layout passes testing regarding electrostatic discharge.
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