发明授权
US07515487B2 Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same
有权
用于降低待机电流的内部参考电压发生电路和包括其的半导体存储器件
- 专利标题: Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same
- 专利标题(中): 用于降低待机电流的内部参考电压发生电路和包括其的半导体存储器件
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申请号: US11567826申请日: 2006-12-07
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公开(公告)号: US07515487B2公开(公告)日: 2009-04-07
- 发明人: Young-Hun Seo , Dong-Il Seo , Kyu-Chan Lee , Jong-Hyun Choi
- 申请人: Young-Hun Seo , Dong-Il Seo , Kyu-Chan Lee , Jong-Hyun Choi
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 代理机构: F. Chau & Assoc., LLC
- 优先权: KR10-2005-0135870 20051230
- 主分类号: G11C5/14
- IPC分类号: G11C5/14
摘要:
An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.