Invention Grant
US07521380B2 Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors
有权
制造具有窄间距和宽间距晶体管的应力增强型半导体器件的方法
- Patent Title: Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors
- Patent Title (中): 制造具有窄间距和宽间距晶体管的应力增强型半导体器件的方法
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Application No.: US11738828Application Date: 2007-04-23
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Publication No.: US07521380B2Publication Date: 2009-04-21
- Inventor: Andrew M. Waite , Scott Luning , Frank (Bin) Yang
- Applicant: Andrew M. Waite , Scott Luning , Frank (Bin) Yang
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469

Abstract:
A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.
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