发明授权
US07526748B2 Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium
失效
设计图案数据准备方法，掩模图案数据准备方法，掩模制造方法，半导体器件制造方法和程序记录介质
- 专利标题： Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium
- 专利标题（中）： 设计图案数据准备方法，掩模图案数据准备方法，掩模制造方法，半导体器件制造方法和程序记录介质
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申请号： US11200176申请日： 2005-08-10
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公开(公告)号： US07526748B2公开(公告)日： 2009-04-28
- 发明人: Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
- 申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2004-233615 20040810
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.
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