Invention Grant
US07531413B2 Method of forming transistor having channel region at sidewall of channel portion hole
失效
在通道部分孔的侧壁处形成具有沟道区的晶体管的方法
- Patent Title: Method of forming transistor having channel region at sidewall of channel portion hole
- Patent Title (中): 在通道部分孔的侧壁处形成具有沟道区的晶体管的方法
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Application No.: US11156271Application Date: 2005-06-17
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Publication No.: US07531413B2Publication Date: 2009-05-12
- Inventor: Soo-Ho Shin , Jin-Woo Lee , Eun-Cheol Lee
- Applicant: Soo-Ho Shin , Jin-Woo Lee , Eun-Cheol Lee
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR10-2004-0045145 20040617
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/3205

Abstract:
According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern.
Public/Granted literature
- US20050282343A1 Method of forming transistor having channel region at sidewall of channel portion hole Public/Granted day:2005-12-22
Information query
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