发明授权
US07536513B2 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state
有权
数据处理系统，缓存系统和方法，用于基于标记的高速缓存状态在不引用低级缓存的情况下在互连结构上发出请求
- 专利标题： Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state
- 专利标题（中）： 数据处理系统，缓存系统和方法，用于基于标记的高速缓存状态在不引用低级缓存的情况下在互连结构上发出请求
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申请号： US11095734申请日： 2005-03-31
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公开(公告)号： US07536513B2公开(公告)日： 2009-05-19
- 发明人: Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Jeffrey A. Stuecheli
- 申请人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Jeffrey A. Stuecheli
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Dillon & Yudell LLP
- 主分类号： G06F13/00
- IPC分类号： G06F13/00 ; G06F13/28 ; G06F12/00
摘要：
In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.