发明授权
US07539840B2 Handling concurrent address translation cache misses and hits under those misses while maintaining command order
失效
在维护命令顺序的同时,处理并发地址转换高速缓存未命中和命中
- 专利标题: Handling concurrent address translation cache misses and hits under those misses while maintaining command order
- 专利标题(中): 在维护命令顺序的同时,处理并发地址转换高速缓存未命中和命中
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申请号: US11420884申请日: 2006-05-30
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公开(公告)号: US07539840B2公开(公告)日: 2009-05-26
- 发明人: John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
- 申请人: John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Joan Pennington
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
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