发明授权
US07541287B2 Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method
有权
在通过该方法制造的载体,载体和半导体晶片的两侧加工半导体晶片的方法
- 专利标题: Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method
- 专利标题(中): 在通过该方法制造的载体,载体和半导体晶片的两侧加工半导体晶片的方法
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申请号: US11487652申请日: 2006-07-17
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公开(公告)号: US07541287B2公开(公告)日: 2009-06-02
- 发明人: Ruediger Schmolke , Thomas Buschhardt , Gerhard Heier , Guido Wenski
- 申请人: Ruediger Schmolke , Thomas Buschhardt , Gerhard Heier , Guido Wenski
- 申请人地址: DE Munich
- 专利权人: Siltronic AG
- 当前专利权人: Siltronic AG
- 当前专利权人地址: DE Munich
- 代理机构: Brooks Kushman P.C.
- 优先权: DE102005034119 20050721
- 主分类号: H01L21/302
- IPC分类号: H01L21/302
摘要:
A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
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