A shift register includes M (M is an integer larger than two) stages of transfer elements and a control circuit. The M stages of the transfer elements transfer N (M>N, N is an integer larger than one) data signals sequentially input within one cycle. To the control circuit, N clock signals and a control signal are input within the one cycle and the control circuit supplies a shift clock signal to N stages of the transfer elements among the M stages of the transfer elements and supplies a skip fixed logic signal to (M−N) stages of the transfer elements among the M stages of the transfer elements based on the control signal.