Invention Grant
- Patent Title: Calibration techniques for frequency synthesizers
- Patent Title (中): 频率合成器的校准技术
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Application No.: US10092669Application Date: 2002-03-06
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Publication No.: US07546097B2Publication Date: 2009-06-09
- Inventor: Jeremy D. Dunworth , Brett C. Walker
- Applicant: Jeremy D. Dunworth , Brett C. Walker
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Bruce Greenhaus; Jonathan T. Velasco; Thomas R. Rouse
- Main IPC: H04B1/04
- IPC: H04B1/04 ; H04B1/18

Abstract:
In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.
Public/Granted literature
- US20030171105A1 Calibration techniques for frequency synthesizers Public/Granted day:2003-09-11
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