Invention Grant
US07550315B2 Method for fabricating semiconductor package with multi-layer die contact and external contact
有权
用于制造具有多层模接触和外部接触的半导体封装的方法
- Patent Title: Method for fabricating semiconductor package with multi-layer die contact and external contact
- Patent Title (中): 用于制造具有多层模接触和外部接触的半导体封装的方法
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Application No.: US11781256Application Date: 2007-07-22
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Publication No.: US07550315B2Publication Date: 2009-06-23
- Inventor: Victor Tan Cher ′Khng , Lee Kian Chai
- Applicant: Victor Tan Cher ′Khng , Lee Kian Chai
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agent Stephen A. Gratton
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate. A method for fabricating the package includes the step of depositing the different layers for the metal bumps using electroless and electrolytic deposition, and then etching the different layers to shape the metal bumps.
Public/Granted literature
- US20070262469A1 METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE WITH MULTI-LAYER DIE CONTACT AND EXTERNAL CONTACT Public/Granted day:2007-11-15
Information query
IPC分类: