Invention Grant
- Patent Title: Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage
- Patent Title (中): 评估集成电路设计和结构中充电损坏潜力的方法,以防止充电损坏
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Application No.: US11749775Application Date: 2007-05-17
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Publication No.: US07560345B2Publication Date: 2009-07-14
- Inventor: Terence B. Hook , Jeffrey Scott Zimmerman
- Applicant: Terence B. Hook , Jeffrey Scott Zimmerman
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent W. Riyon Harding
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.
Public/Granted literature
Information query
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