发明授权
- 专利标题: Fast parity scan of memory arrays
- 专利标题(中): 快速奇偶校验扫描存储器阵列
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申请号: US11315971申请日: 2005-12-21
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公开(公告)号: US07565597B1公开(公告)日: 2009-07-21
- 发明人: Kenneth Branth , Kee W. Park
- 申请人: Kenneth Branth , Kee W. Park
- 申请人地址: US CA San Jose
- 专利权人: Integrated Device Technology, Inc.
- 当前专利权人: Integrated Device Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Glass & Associates
- 代理商 Michael R. Hardaway
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.
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