发明授权
- 专利标题： Integrated fault output/fault response delay circuit
- 专利标题（中）： 集成故障输出/故障响应延迟电路
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申请号： US11672739申请日： 2007-02-08
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公开(公告)号： US07573393B2公开(公告)日： 2009-08-11
- 发明人: David J. Haas , Jonathan Lamarre , Michael C. Doogue
- 申请人： David J. Haas , Jonathan Lamarre , Michael C. Doogue
- 申请人地址： US MA Worcester
- 专利权人： Allegro Microsystems, Inc.
- 当前专利权人： Allegro Microsystems, Inc.
- 当前专利权人地址： US MA Worcester
- 代理机构： Daly, Crowley, Mofford & Durkee, LLP
- 主分类号： G08B21/00
- IPC分类号： G08B21/00 ; H02H3/00 ; G01R31/14
摘要：
A time delay fault device includes an integrated circuit (IC) having an electronic circuit having a fault indicator signal output and a time delay circuit having an input connected to the fault indicator signal output and an output to provide a delayed fault indicator signal output, the time delay circuit being responsive to an external voltage from a resistor capacitor network coupled to the delayed fault indicator signal output to set the time delay of the delayed fault indicator signal.
公开/授权文献
- US20080191865A1 INTEGRATED FAULT OUTPUT/FAULT RESPONSE DELAY CIRCUIT 公开/授权日：2008-08-14
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