发明授权
- 专利标题: High-speed verifiable semiconductor memory device
- 专利标题(中): 高速可验证半导体存储器件
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申请号: US12210585申请日: 2008-09-15
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公开(公告)号: US07573750B2公开(公告)日: 2009-08-11
- 发明人: Noboru Shibata
- 申请人: Noboru Shibata
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权: JP2004-359029 20041210
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.
公开/授权文献
- US20090016117A1 HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE 公开/授权日:2009-01-15
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