发明授权
US07577797B2 Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
失效
数据处理系统,缓存系统和基于组合响应精确形成无效一致性状态的方法
- 专利标题: Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
- 专利标题(中): 数据处理系统,缓存系统和基于组合响应精确形成无效一致性状态的方法
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申请号: US11388016申请日: 2006-03-23
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公开(公告)号: US07577797B2公开(公告)日: 2009-08-18
- 发明人: Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
- 申请人: Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Dillon & Yudell LLP
- 主分类号: G06F13/00
- IPC分类号: G06F13/00 ; G06F13/28
摘要:
A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination. At least the first and second partial responses are accumulated to obtain a combined response for the exclusive access request. The combined response includes an indication of whether or not a highest point of coherency and a memory controller of a home system memory for the target address reside within a same coherency domain. The first cache memory updates the coherency state field from the first coherency state to a second coherency state in response to the indication in the combined response.
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