发明授权
- 专利标题: Mechanisms to prevent undesirable bus behavior
- 专利标题(中): 防止不必要的总线行为的机制
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申请号: US10444154申请日: 2003-05-22
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公开(公告)号: US07577877B2公开(公告)日: 2009-08-18
- 发明人: Theodore F. Emerson , Phyllis L. Bongain , Cesar Buentello , Jennifer C. Kleiman , Doron Chosnek , Robert L. Noonan , David F. Heinrich
- 申请人: Theodore F. Emerson , Phyllis L. Bongain , Cesar Buentello , Jennifer C. Kleiman , Doron Chosnek , Robert L. Noonan , David F. Heinrich
- 申请人地址: US TX Houston
- 专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人地址: US TX Houston
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
A system includes proxy logic which detects situations which, unless action is taken, would result in undesirable bus behavior. In one embodiment, the target device of a bus cycle includes proxy logic which determines when the target device is unable to respond correctly to a bus cycle. In this situation, the proxy logic blocks a bus signal from being received by the addressed logic in the target device, thereby preventing the target device from responding at all. In another embodiment, proxy logic is located external to the target device and determines when the target device has not responded to a cycle intended for it. When this condition has occurred, the proxy logic responds to the cycle before the bus's subtractive decode agent has a chance to claim the cycle. The proxy logic's response may be to return bogus data or terminate or abort the cycle.
公开/授权文献
- US20050060468A1 Mechanisms to prevent undesirable bus behavior 公开/授权日:2005-03-17
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