发明授权
US07589367B2 Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines
有权
包括全局工作线，本地工作线，全局位线和局部位线的半导体存储器件中的布局结构
- 专利标题： Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines
- 专利标题（中）： 包括全局工作线，本地工作线，全局位线和局部位线的半导体存储器件中的布局结构
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申请号： US11316871申请日： 2005-12-27
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公开(公告)号： US07589367B2公开(公告)日： 2009-09-15
- 发明人: Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
- 申请人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
- 申请人地址： KR Suwon-si, Gyeonggi-do
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR Suwon-si, Gyeonggi-do
- 代理机构： Volentine & Whitt, PLLC
- 优先权： KR10-2005-0029369 20050408
- 主分类号： H01L27/108
- IPC分类号： H01L27/108
摘要：
A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.