发明授权
- 专利标题: PVT compensated auto-calibration scheme for DDR3
- 专利标题(中): 用于DDR3的PVT补偿自动校准方案
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申请号: US11936036申请日: 2007-11-06
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公开(公告)号: US07590008B1公开(公告)日: 2009-09-15
- 发明人: Manoj B. Roge , Andrew Bellis , Philip Clarke , Joseph Huang , Michael H. M. Chu , Yan Chong
- 申请人: Manoj B. Roge , Andrew Bellis , Philip Clarke , Joseph Huang , Michael H. M. Chu , Yan Chong
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Townsend and Townsend and Crew LLP
- 代理商 J. Matthew Zigmant
- 主分类号: G11C7/00
- IPC分类号: G11C7/00
摘要:
Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.