发明授权
US07592265B2 Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor
有权
修整硬掩模层的方法，在MOS晶体管中制造栅极的方法和用于制造MOS晶体管中的栅极的堆叠
- 专利标题： Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor
- 专利标题（中）： 修整硬掩模层的方法，在MOS晶体管中制造栅极的方法和用于制造MOS晶体管中的栅极的堆叠
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申请号： US11620028申请日： 2007-01-04
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公开(公告)号： US07592265B2公开(公告)日： 2009-09-22
- 发明人: Meng-Jun Wang , Yi-Hsing Chen , Min-Chieh Yang , Jiunn-Hsiung Liao
- 申请人： Meng-Jun Wang , Yi-Hsing Chen , Min-Chieh Yang , Jiunn-Hsiung Liao
- 申请人地址： TW Hsin-Chu
- 专利权人： United Microelectronics Corp.
- 当前专利权人： United Microelectronics Corp.
- 当前专利权人地址： TW Hsin-Chu
- 代理商 Winston Hsu
- 主分类号： H01L21/302
- IPC分类号： H01L21/302 ; H01L21/461
摘要：
A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.
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