发明授权
US07595251B2 Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby
有权
制造具有对准键的半导体器件和由此制造的半导体器件的方法
- 专利标题: Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby
- 专利标题(中): 制造具有对准键的半导体器件和由此制造的半导体器件的方法
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申请号: US12325694申请日: 2008-12-01
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公开(公告)号: US07595251B2公开(公告)日: 2009-09-29
- 发明人: Min-Hee Cho , Yoo-Sang Hwang , Byung-Hyun Lee
- 申请人: Min-Hee Cho , Yoo-Sang Hwang , Byung-Hyun Lee
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Mills & Onello, LLP.
- 优先权: KR10-2004-0076612 20040923
- 主分类号: H01L21/76
- IPC分类号: H01L21/76
摘要:
In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.
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