发明授权
- 专利标题： Method of forming a metal line of a semiconductor device
- 专利标题（中）： 形成半导体器件的金属线的方法
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申请号： US11646925申请日： 2006-12-27
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公开(公告)号： US07601632B2公开(公告)日： 2009-10-13
- 发明人: Eun Soo Kim , Cheol Mo Jeong , Seung Hee Hong
- 申请人： Eun Soo Kim , Cheol Mo Jeong , Seung Hee Hong
- 申请人地址： KR Icheon-Si
- 专利权人： Hynix Semiconductor Inc.
- 当前专利权人： Hynix Semiconductor Inc.
- 当前专利权人地址： KR Icheon-Si
- 代理机构： Marshall, Gerstein & Borun LLP
- 优先权： KR10-2006-0086826 20060908
- 主分类号： H01L21/00
- IPC分类号： H01L21/00
摘要：
A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.
公开/授权文献
- US20080064204A1 Method of forming a metal line of a semiconductor device 公开/授权日：2008-03-13