Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region

Invention Grant

US07608500B2 Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region 失效

Title translation: 形成半导体器件的方法包括在每个区域上形成控制栅极层并去除低电压区域上的隧道绝缘层的一部分

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Patent Title: Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region
Patent Title (中): 形成半导体器件的方法包括在每个区域上形成控制栅极层并去除低电压区域上的隧道绝缘层的一部分
Application No.: US11671994

Application Date: 2007-02-06
Publication No.: US07608500B2

Publication Date: 2009-10-27
Inventor: Byung-Kwan You , Jun-Eui Song , Gyeong-Hee Kim , Hee-Jueng Lee
Applicant: Byung-Kwan You , Jun-Eui Song , Gyeong-Hee Kim , Hee-Jueng Lee
Applicant Address: KR Suwon-si, Gyeonggi-do
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR Suwon-si, Gyeonggi-do
Agency: Marger Johnson & McCollom, P.C.
Priority: KR10-2006-0011846 20060207
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/8234

Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region

Abstract:

Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract(Chinese):

提供一种形成半导体器件的方法。在具有单元区域和低电压区域的基板上形成隧道绝缘层。第一和第二电荷存储栅极图案（例如，浮栅图案）分别形成在电池和低电压区域的隧道绝缘层上。依次在基板上形成阻挡绝缘层和控制栅极导电层。除去低电压区域的控制栅极导电层，阻挡绝缘层，第二浮栅图案和隧道绝缘层，露出低电压区域的基板。低压栅极绝缘层形成在暴露的基板上。在低压栅极绝缘层上形成低压栅极导电图案。

Public/Granted literature

US20070184606A1 METHOD OF FORMING SEMICONDUCTOR DEVICE Public/Granted day:2007-08-09

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS