Invention Grant
- Patent Title: Fabricating substrates having low inductance via arrangements
- Patent Title (中): 通过布置制造具有低电感的基板
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Application No.: US11355713Application Date: 2006-02-16
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Publication No.: US07614141B2Publication Date: 2009-11-10
- Inventor: Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Roger D. Weekly
- Applicant: Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Roger D. Weekly
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen J. Walder, Jr.; Diana R. Gerhardt
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.
Public/Granted literature
- US20070187468A1 Low inductance via arrangement for multilayer ceramic substrates Public/Granted day:2007-08-16
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