发明授权
US07615454B2 Embedded stressed nitride liners for CMOS performance improvement 有权
嵌入式应力氮化物衬垫可提高CMOS性能

Embedded stressed nitride liners for CMOS performance improvement
摘要:
The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 Mpa.
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