Invention Grant
US07615462B2 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
有权
通过蚀刻在三维(3-D)晶圆到晶片垂直堆叠中的硅(Si)蚀刻停止层
- Patent Title: Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
- Patent Title (中): 通过蚀刻在三维(3-D)晶圆到晶片垂直堆叠中的硅(Si)蚀刻停止层
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Application No.: US11528986Application Date: 2006-09-27
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Publication No.: US07615462B2Publication Date: 2009-11-10
- Inventor: Sarah E. Kim , R. Scott List , Tom Letson
- Applicant: Sarah E. Kim , R. Scott List , Tom Letson
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/44

Abstract:
A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
Public/Granted literature
- US20070020805A1 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack Public/Granted day:2007-01-25
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